- Author :
- Publsiher :
- Release : 01 January 1970
- ISBN :
- Pages : pages
- Rating : /5 from ratings
Architecture Design for Soft Errors provides a comprehensive description of the architectural techniques to tackle the soft error problem. It covers the new methodologies for quantitative analysis of soft errors as well as novel, cost-effective architectural techniques to mitigate them. To provide readers with a better grasp of the broader problem definition and solution space, this book also delves into the physics of soft errors and reviews current circuit and software mitigation techniques. There are a number of different ways
Soft errors are a multifaceted issue at the crossroads of applied physics and engineering sciences. Soft errors are by nature multiscale and multiphysics problems that combine not only nuclear and semiconductor physics, material sciences, circuit design, and chip architecture and operation, but also cosmic-ray physics, natural radioactivity issues, particle detection, and related instrumentation. Soft Errors: From Particles to Circuits addresses the problem of soft errors in digital integrated circuits subjected to the terrestrial natural radiation environment—one of the most
This book describes the benefits and drawbacks inherent in the use of virtual platforms (VPs) to perform fast and early soft error assessment of multicore systems. The authors show that VPs provide engineers with appropriate means to investigate new and more efficient fault injection and mitigation techniques. Coverage also includes the use of machine learning techniques (e.g., linear regression) to speed-up the soft error evaluation process by pinpointing parameters (e.g., architectural) with the most substantial impact on the
Shrinking feature size and diminishing supply voltage are making circuits sensitive to supply voltage fluctuations within the microprocessor, caused by normal workload activity changes. If left unattended, voltage fluctuations can lead to timing violations or even transistor lifetime issues that degrade processor robustness. Mechanisms that learn to tolerate, avoid, and eliminate voltage fluctuations based on program and microarchitectural events can help steer the processor clear of danger, thus enabling tighter voltage margins that improve performance or lower power consumption. We
"This book covers aspects of system design and efficient modelling, and also introduces various fault models and fault mechanisms associated with digital circuits integrated into System on Chip (SoC), Multi-Processor System-on Chip (MPSoC) or Network on Chip (NoC)"--
This book constitutes the refereed proceedings of the 12th International Haifa Verification Conference, HVC 2016, held in Haifa, Israel in November 2016. The 13 revised full papers and one tool paper presented were carefully reviewed and selected from 26 submissions. They are dedicated to advance the state of the art and state of the practice in verification and testing and are discussing future directions of testing and verification for hardware, software, and complex hybrid systems.
This book equips readers with tools for computer architecture of high performance, low power, and high reliability memory hierarchy in computer systems based on emerging memory technologies, such as STTRAM, PCM, FBDRAM, etc. The techniques described offer advantages of high density, near-zero static power, and immunity to soft errors, which have the potential of overcoming the “memory wall.” The authors discuss memory design from various perspectives: emerging memory technologies are employed in the memory hierarchy with novel architecture modification; hybrid
This book describes the state-of-the-art in energy efficient, fault-tolerant embedded systems. It covers the entire product lifecycle of electronic systems design, analysis and testing and includes discussion of both circuit and system-level approaches. Readers will be enabled to meet the conflicting design objectives of energy efficiency and fault-tolerance for reliability, given the up-to-date techniques presented.
The advent of multi-core architectures and cloud-computing has brought parallel programming into the mainstream of software development. Unfortunately, writing scalable parallel programs using traditional lock-based synchronization primitives is well known to be a hard, time consuming and error-prone task, mastered by only a minority of specialized programmers. Building on the familiar abstraction of atomic transactions, Transactional Memory (TM) promises to free programmers from the complexity of conventional synchronization schemes, simplifying the development and verification of concurrent programs, enhancing code reliability,
This book introduces new compilation techniques, using the polyhedron model for the resource-adaptive parallel execution of loop programs on massively parallel processor arrays. The authors show how to compute optimal symbolic assignments and parallel schedules of loop iterations at compile time, for cases where the number of available cores becomes known only at runtime. The compile/runtime symbolic parallelization approach the authors describe reduces significantly the runtime overhead, compared to dynamic or just‐in-time compilation. The new, on‐demand fault‐
This book constitutes the refereed proceedings of the 15th International Conference on Parallel Computing, Euro-Par 2009, held in Delft, The Netherlands, in August 2009. The 85 revised papers presented were carefully reviewed and selected from 256 submissions. The papers are organized in topical sections on support tools and environments; performance prediction and evaluation; scheduling and load balancing; high performance architectures and compilers; parallel and distributed databases; grid, cluster, and cloud computing; peer-to-peer computing; distributed systems and algorithms; parallel and distributed programming; parallel numerical algorithms;
This Open Access book introduces readers to many new techniques for enhancing and optimizing reliability in embedded systems, which have emerged particularly within the last five years. This book introduces the most prominent reliability concerns from today’s points of view and roughly recapitulates the progress in the community so far. Unlike other books that focus on a single abstraction level such circuit level or system level alone, the focus of this book is to deal with the different reliability
This two-volume set LNICST 357-358 constitutes the post-conference proceedings of the 11th EAI International Conference on Wireless and Satellite Services, WiSATS 2020, held in Nanjing, China, in September 2020. The 91 full papers and workshop papers were carefully reviewed and selected from 200 submissions. Part I - LNICST 357 - details original research and results of wireless and satellite technology for a smarter global communication architecture. The theme of WISATS 2020 is “Intelligent Wireless and Satellite Communications for Beyond 5G”. Part II – LNICST 358 - presents 6 workshop
What the experts have to say about Model-Based Testing for Embedded Systems: "This book is exactly what is needed at the exact right time in this fast-growing area. From its beginnings over 10 years ago of deriving tests from UML statecharts, model-based testing has matured into a topic with both breadth and depth. Testing embedded systems is a natural application of MBT, and this book hits the nail exactly on the head. Numerous topics are presented clearly, thoroughly, and concisely in
This book constitutes the proceedings of the 30th International Conference on Architecture of Computing Systems, ARCS 2017, held in Vienna, Austria, in April 2017. The 19 full papers presented in this volume were carefully reviewed and selected from 42 submissions. They were organized in topical sections entitled: resilience; accelerators; performance; memory systems; parallelism and many-core; scheduling; power/energy.